A low cost test pattern generator for test-per-clock BIST scheme
نویسندگان
چکیده
منابع مشابه
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roug...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2010
ISSN: 1349-2543
DOI: 10.1587/elex.7.672